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YOKOHAMA, Japan--(BUSINESS WIRE)--Feb. 1, 2001--Electronic Design and Solution Fair 2001--Virtual Silicon Technology, Inc. announced today that Hitachi, Ltd. has adopted its phase locked loop (PLL) compiler for 0.18 micron technology. Virtual Silicon's PLL compiler reduces design time for Hitachi's complex system-on-chips requiring complex clocking schemes. The PLL compiler incorporates innovative test schemes to reduce test costs of complex analog components.

``All of our complex SOC designs in low-power consumer and high-speed networking demand precise control of clocking schemes,'' said Kotaro Nishimura, general manager of the 1st System LSI Business Operation, Semiconductor & Integrated Circuits at Hitachi. ``Our ASIC customers will be able to achieve their low-power and performance goals using the capabilities of the Virtual Silicon PLL compiler.''

``Today's SOC designers require robust PLL technology to meet the complex clocking requirements for high speed communications and low-power consumer markets,'' said Mahesh Tirupattur, vice president of Pacific Rim operation, Virtual Silicon Technology. ``The eSi-PLL compiler offers system designers a high-degree of flexibility to choose PLLs that address those needs in a wide range of applications.''

Proven PLL Circuit Design and Compiler Methodology

The PLL circuit design has been proven with successful customer designs in several different 0.25, 0.18 and 0.15 micron processes. The PLL operates in frequencies in excess of one gigahertz, and has demonstrated low jitter characteristics of less than 75 picoseconds.

The eSi-PLL(TM) phase-locked loop compiler greatly reduces system designers' effort to integrate complex analog components during SOC design. The compiler generates a custom PLL macro based on user-specified frequencies and duty cycles. The eSi-PLL compiler generates design views that support industry standard EDA tools including Synopsys, Cadence, Mentor and Avant!.

Modular PLL Design Reduces Die Size and Increases Noise Immunity

The eSi-PLL compiler layout is designed to minimize die area by fitting inside the I/O pad ring, resulting in zero area usage in the core logic region. Utilizing proprietary technology licensed from Analog Bits, the analog components such as loop-filter, oscillator, by-pass circuitry are fully integrated and pre-connected to produce high-precision clock signals. The eSi-PLL incorporates a unique voltage-controlled oscillator (VCO) that offers excellent noise immunity and eliminates the need for external band-gap reference type circuitry.

``This announcement demonstrates the further acceptance of Virtual Silicon's mixed-signal technology leadership and unique compiler solution for complex PLLs,'' said Taylor Scanlon, chief executive officer, Virtual Silicon Technology. ``The eSi-PLL compiler offers a complete, automated, silicon proven solution for one of the most challenging areas of today's SOC designs.''

About Virtual Silicon Technology

Virtual Silicon Technology is a leading supplier of embedded semiconductor technology to manufacturers and designers of complex systems-on-chip. We provide process-intensive embedded components including standard cell libraries, I/Os, SRAM compilers, PLL compilers and embedded EEPROM solutions. The company provides application-specific, process-specific and foundry-portable versions of its Silicon Ready libraries and hard IP to semiconductor manufacturers and foundries, ASSP designers, and systems developers who demand the highest quality, maximum performance and optimum densities for their semiconductor innovations. For more information on Virtual Silicon Technology and its products, please direct customer inquiries to Mahesh Tirupattur at (408) 548-2726, email address: mahesh@virtual-silicon.com or go to www.virtual-silicon.com.

eSilicon, eSi-Route, eSi-Pad, eSi-RAM, eSi-ROM, eSi-PLL, The Heart of Great Silicon, Silicon Ready, IP Ambassador, Design Service Ambassador, and Virtual Silicon are trademarks of Virtual Silicon Technology, Inc.

     Virtual Silicon Technology
     Mahesh Tirupattur, 408/548-2726
     mahesh@virtual-silicon.com
      or
     VitalCom Marketing and PR
     Karen Tyrrell, 650/637-8212 Ext. 204
     karen@vitalcompr.com